1. Field of the Invention
The present invention relates generally to photolithography techniques which are used during the fabrication of semiconductor devices. More specifically, the present invention relates to a technique which uses multiple mappings of a critical dimension of selected features that are formed on wafer during formation of integrated circuits (IC), to enable optical proximity correction in an efficient manner and with particular regard to mitigating effects which are encountered during the various steps which are carried during the constructive processes.
2. Description of the Related Art
The minimum feature sizes of integrated circuits (ICs) have been constantly shrinking. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography which involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers (e.g., regions of substrate, polysilicon, dielectric or the like).
An integral component of a photolithographic apparatus is a xe2x80x9creticlexe2x80x9d which contains a pattern corresponding to features at a layer in an IC design. These devices typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which forms part of a optics arrangement of a xe2x80x9cstepperxe2x80x9d apparatus. Located beneath the optics in which the reticle is disposed, is a table. The table is provided with a vacuum clutch or the like and is operatively connected with servo mechanisms to be movable in three mutually opposed directions with respect to optical arrangement in which the reticle is disposed. This allows a resist covered wafer which is supported on the table to be selectively moved with respect to the optics so that the resist coating can be repeatedly imprinted with an image produced by the reticle.
When the radiation from the radiation source is directed onto the reticle, light passes through the uncovered glass portions and projects onto the resist covered silicon wafer. In this manner, an image which is produced by the reticle is imprinted onto the resist.
The resist or photoresist as it is sometimes called, is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface. The resist material is classified as either positive or negative depending on how it responds to light radiation. Positive resist, when exposed to radiation becomes more soluble and is thus more easily removed in a development process. As a result, a developed positive resist contains a resist pattern corresponding to the dark regions on the reticle. Negative resist, on the other hand, becomes less soluble when exposed to radiation. Consequently, a developed negative resist contains a pattern corresponding to the transparent regions of the reticle. For simplicity, the following discussion is in connection with positive resists, it being understood that negative resists may be substituted therefor given that the appropriate adjustments are made. For further information on IC fabrication and resist development methods, reference may be made to a book entitled Integrated Circuit Fabrication Technology by David J. Elliot, McGraw Hill, 1989.
One problem associated with photolithography is that light passing through a reticle tends to be refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process.
To overcome this problem, a reticle correction technique known as optical proximity correction (xe2x80x9cOPCxe2x80x9d) has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to resolve the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated using software to identify regions where optical distortion is apt to result. Optical proximity correction is then applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they can not be ignored in layouts having features less than about 1 micron.
The OPC process is generally performed by scanning a digital version of an IC layout design to identify feature dimensions, interfeature spacing, feature orientation, etc. The scanning process may proceed across the IC layout design in a rasterized fashion to cover the entire pattern. In some IC layout designs, it may also be necessary to conduct raster scans in the two or more directions (e.g., horizontal, vertical, and one or more diagonal directions). In some cases, the OPC computations may include generating a detailed computer model of a reticle image known as a Fast Aerial Image of Mask (FAIM). This image is then itself evaluated to determine where to make reticle corrections.
However, a drawback is encountered in that the process of performing OPC on modern IC layout designs having many features can be computationally intensive. In fact, OPC can sometimes be too great for even the most advanced computational resources. Obviously, when FAIM models are used, the computational difficulty increases significantly.
Further, one specific type of optical distortion requiring some form of correction is called xe2x80x9creflective notching.xe2x80x9d This form of distortion arises not from the interaction of light with the reticle pattern itself, but from the interaction of light with structures on the wafer surface. Specifically, light directed onto topographical variations introduced on a wafer surface at certain stages in the IC fabrication process (e.g., field oxide formation) scatters and reflects. As a result, illuminated line patterns crossing over a field oxide/active region interface or other topographically varying surface structure produces notches (reflective nothing).
This reflective notching, of course, tends to degrade integrated circuit performance. For example, the current carrying characteristics of a polysilicon line will deviate from design, in these narrow regions, potentially leading to hot spots in the polysilicon line. In some cases, such problems may render the resulting integrated circuit unusable. The speed and performance of a complex circuit, such as a microprocessor is, of course, adversely effected by such imperfections.
Accordingly, despite quite sophisticated advances in reticle inspection/correction, it is necessary to achieve further development in reticle adjustment and design in order to overcome the problems such as the above mentioned reflective notching.
The present invention is based on a technique wherein mapping is carried out at each of a select number of production stages, and wherein critical dimension (CD) data, which is accumulated during each of the mappings, is used to determine what adjustments can be made to reticle which is used in the production, to ensure that the closest possible adherence to the design requirements is achieved.
In other words, a feedback control data base is enabled. For example, mapping of results of the etching are examined and a line width or corner is too great or too small, or the configurations of given features are not as good as is required to assure the best performance of the device (e.g., features necessary to optimize the speed performance of a microprocessor for example) then determined what adjustments can be made to the process at each of the stages which are involved in the process, and to instigate changes which will enable improvements to be made and for a better product to be realized.
In particular, this technique, in accordance with the present invention, enables the design of an incoming reticle to be checked/modified so as to achieve the best possible results. Once the reticle is modified and its performance is assured, the amount of mapping which is used during actual production runs can be reduced to that which is necessary to determine that the process is running properly and that new reticle is functioning optimally.
More specifically, a first aspect of the present innovation resides in a method of improving IC fabrication comprising the steps of: mapping the critical dimensions of a predetermined plurality of features at each of a predetermined number of stages of production of an IC; comparing the data collected at each of the mappings; and determining, from the comparison, what changes are required in a selected one of the production stages to bring the critical dimension of the predetermined features into agreement with a predetermined set of design critical dimension. These predetermined features comprise ring oscillators, turning forks, test transistors, and WET transistors.
Another aspect of the present invention resides in a method of qualifying a reticle comprising the steps of: disposing a reticle in a stepper and exposing at least one exposure field using the reticle; mapping the critical dimension of all features the impact speed and performance of the IC, including ring oscillators, turning forks, test transistors, and WET transistors, which are located in the exposure field; comparing the mapped critical dimension with a set of corresponding prerequisite critical dimension values; and modifying the reticle in order to bring the critical dimension which are derived using the mapping into accordance with a difference between the mapped critical dimension and the prerequisite critical dimension values.
In this method the substrate comprises a wafer and wherein the coating of photo resist is formed to substantially cover an upper surface thereof; and the image is impressed a plurality of times in a predetermined sequence of preset positions to form a predetermined number of exposure fields on the coating by moving the wafer to a series of predetermined positions with respect to the reticle.
The critical dimension data in this aspect is limited to data pertaining to a predetermined number of critical elements comprising oscillators, turning forks, test transistors, and WET transistors and/or other elements which determine the speed of operation of the processors which are created by an etching step.
Another aspect of the invention resides in a method of qualifying a reticle comprising the steps of: mapping predetermined features of a reticle to determine a first set of critical dimension data; mounting the reticle in a stepper and operating the stepper to move the substrate into a predetermined position with respect to the reticle; impressing the image produced by the reticle onto a layer of photo resist formed on a substrate a plurality of times to form a corresponding plurality of exposure fields; removing the portion of the photo resist effected by the image impression to leave a photo resist mask pattern; mapping the predetermined features as they are formed in the photo resist mask pattern for each of selected exposure fields selected from among the plurality of exposure fields, to determine a second predetermined set of critical dimension data for the pattern; etching the substrate through the photo resist mask pattern; removing the photo resist mask pattern to reveal an etched pattern formed in the substrate; mapping the predetermined features in the etched pattern corresponding to each of the selected exposure fields and recording a third set of critical dimension data; comparing the first, and at least one of the second and third sets of critical dimension data with each other and/or a predetermined set of standard critical dimension data values; and determining an adjustment to the reticle which is required to reduce a difference between the third set of critical dimension data and the predetermined set of critical dimension data.
In accordance with this aspect the substrate comprises a wafer and wherein the step of impressing comprises impressing a predetermined plurality of images at a center portion of the wafer. The predetermined features comprise ring oscillators, turning forks, test transistors, and WET transistors.